LIBRARY IEEE;         
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

USE WORK.TYPES.ALL;

entity MEM_WB is
    port(
        clock, reset    : IN  STD_LOGIC;
        RegWrite_in     : IN  STD_LOGIC;
        MemtoReg_in     : IN  STD_LOGIC;
        ReadData_in     : IN  MEMDATA;
        ALU_result_in   : IN  MEMDATA;
        WrAddr_in       : IN  REGADDR;
        RegWrite_out    : OUT STD_LOGIC;
        MemtoReg_out    : OUT STD_LOGIC;
        ReadData_out    : OUT MEMDATA;
        ALU_result_out  : OUT MEMDATA;
        WrAddr_out      : OUT REGADDR
    );
end MEM_WB;

architecture pipe of MEM_WB is
begin
    process (clock)
    begin
        if rising_edge(clock) then
            RegWrite_out    <= RegWrite_in;
            MemtoReg_out    <= MemtoReg_in;
            ReadData_out    <= ReadData_in;
            ALU_result_out  <= ALU_result_in;
            WrAddr_out      <= WrAddr_in;
        end if;
    end process;
end pipe;

